The present invention relates to methods of semiconductor fabrication. More particularly, the present invention relates to wet etching methods that selectively remove cobalt.
Integrated circuit processing can be generally divided into front end of the line (FEOL), middle of the line (MOL) and back end of the line (BEOL) processes. The FEOL and MOL processing will generally form many layers of logical and functional devices. By way of example, the typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact (CA) formation. Layers of interconnections are formed above these logical and functional layers during the BEOL processing to complete the integrated circuit structure. As such, BEOL processing generally involves the formation of insulators and conductive wiring.
Cobalt is a promising fill material that can be used in FEOL, MOL, and BEOL manufacture of advanced semiconductor devices, for example, as a PMOS fill material in a metal gate, a contact conductor fill, and as a conductor fill material for interconnects. Conventional methods of etching cobalt in these processes generally include wet etching with corrosive and toxic materials or dry etching using plasmas that produce undesirable byproducts, have poor selectivity to other films/materials exposed, or ineffective etch rates.